Gasgoo Munich- the Automotive Semiconductor Ecosystem Conference 2026 hosted by Gasgoo on September 16, Li Weili, a processor architect at Alibaba DAMO Academy, outlined the progress and challenges of RISC-V in automotive electronics. He noted that while RISC-V applications in China and abroad have reached a viable state across four layers—IP, IC, complete systems, and software ecosystems—functional safety development still faces hurdles. These include lengthy process cycles and the difficulty of meeting diagnostic coverage targets for ASIL-B software.Li Weili | Processor Architect, Alibaba DAMO AcademyLi Weili said that developing functional safety products requires an iterative loop of both process and product certification. "Completing this cycle generally takes three to five years." Technically, ASIL-D systems typically employ a Dual-Core Lockstep (DCLS) approach. While the logic is straightforward, it comes at the cost of double the area and double the power consumption. Conversely, ASIL-B systems usually rely on Software Test Library (STL) diagnostics to optimize power, performance, and area (PPA). This demands 90% diagnostic coverage with only a 10% to 20% increase in area—a challenge Li described as "significant."Li detailed the three constraints facing STL development. First is runtime: STL execution cannot disrupt existing functions, meaning individual code segments must be kept within a few thousand cycles to avoid extending interrupt response latency. Second is storage: automotive applications have tight memory budgets, forcing STL to remain compact, which limits the variety of available instructions and test cases. Third is access safety: accessing Device-type I/O hardware can trigger irreversible states, further compressing the scope for software diagnostics.Regarding diagnostic coverage, Li highlighted a critical research finding: there is a significant gap between coverage in Register-Transfer Level (RTL) simulation versus netlist simulation. "The difference is usually more than 5%, potentially reaching 7%, 8%, or even 10%." This implies that achieving 90% coverage at the RTL level may not pass validation at the netlist stage, forcing development teams to target 95% or higher during RTL design. Additionally, internal MCU modules like prediction and prefetch units are difficult for STL instructions to cover directly. Similarly, bus fault injections that cross bus boundaries leave the test environment and are corrected by the external system, resulting in readbacks that always return correct values—both of which complicate the drive to meet coverage targets.Looking ahead, Li called on more vendors to join the RISC-V automotive ecosystem. The goal isn't just to enrich MCU-level IP for ASIL-B and ASIL-D standards, but to develop high-performance computing cores tailored for autonomous driving—ultimately building a richer, more robust ecosystem.